1. Field of the Invention
The present invention relates to a multistage pipeline latch circuit advantageously used in LSI design, and relates in particular to a latch circuit that take into account the timing of the data input and the clock input and a multistage pipeline latch circuit and manufacturing method for the same.
2. Description of the Related Art
Conventionally, in order to form a multistage pipeline latch circuit during LSI design, generally, flip-flop circuits, latch circuits, and the like are used. Here, a pipeline latch circuit denotes a circuit that transmits stored data in sequence using flip-flop circuits, latch circuits, and the like. FIG. 8 is a structural drawing of the packaged state of a two stage pipeline latch circuit formed using flip-flop circuits and latch circuits, and shows the reference clock CLK, the flip-flop FF package, the latch packages (A) to (C), and the latch insertion positions. The reference clock CLK has a clock frequency that can carry at least two clock wavelengths, one at a start point flip-flop 000 and one at an end point flip-flop 002. When the clock frequency is 100 MHz, for example, one cycle of the clock becomes 10 nsec, which cannot be ignored even when compared to the switching speed of a switching transistor, and thus the clock waveform distribution will appear in the wiring pattern that connects the flip-flop circuits and the latch circuits.
The start point flip flop 000, middle flip flop 001, and the end point flip flop 002 are rising edge flip-flops FF. The latch circuit 003 is an LL latch circuit with a through period when the clock is 0 (low) and a hold period when the clock is 1 (high). The latch circuit 004 is an LH latch circuit with a through period when the clock is 1 and a hold period when the clock is 0. Reference numerals 010 to 014 denote logic gates. The clock waveform 020 is the clock waveform CKL input to the flip flop circuits FF and the latch circuits LL and LH.
As shown by the FF package in FIG. 8, in the case of packaging a two stage pipeline using flip flop circuits, the delay of the logic gates between flip flop circuits must fulfill the following Equations. Here, the waveform of the clock is assumed to be ideal. (conditions for the insertion position of the middle flip flop 001)
Ftpd+D010+Fsetxe2x89xa6Tclkxe2x80x83xe2x80x83(1)
Ftpd+D011+Fsetxe2x89xa6Tclkxe2x80x83xe2x80x83(2)
Here, Ftpd and Fset respectively denote the delay time and the setup time of the flip flop circuit, D010 and D011 respectively denote the delay times of logic gate 010 and 011, and Tclk denotes the clock cycle. Using Equations 1 and 2, the logic gates having a maximum delay time of Tclkxe2x88x92Ftpdxe2x88x92Fset can be incorporated between flip flop circuits.
The maximum delay of the logic gates permitted during 2 clock cycles becomes:
xe2x80x83D010+D011=2(Tclkxe2x88x92Ftpdxe2x88x92Fset)xe2x80x83xe2x80x83(3)
There is only one point for the insertion position of the flip flop 001 in order to incorporate logic gates having the delay in Equation 3, and when displaced from this point, the maximum delay of the logic gates (3) must be decreased to less than Equation 3. In the design of flip flop circuits, there is a wait from the input of the data into the flip flop circuit until the rise of the clock, and when this waiting time increases, the maximum delay of the logic gates (3) is reduced.
Next, as shown in FIG. 8, in the case of packaging the two stage pipeline using flip flop circuits and latch circuits, data input into the latch circuits is fixed during the through period. When carried out using this structure, the waiting for the clock that occurs at the middle flip flop circuit package does not occur at the latch circuits. The maximum delay time permitted in two clock cycles becomes:
D012+D013+D014=2Tclkxe2x88x922Ldelxe2x88x92Ftpdxe2x88x92Fsetxe2x80x83xe2x80x83(4)
Here, Ldel denotes the through delay time of the latch circuit, and D012, D013 and D014 respectively denote the delay times of the logic gates 012, 013, and 014. The insertion positions of latch circuits 003 and 004 for incorporating logic gates having the delay of Equation 4 have a permitted width, and the data input to the latch circuits can be defined during the through period.
The conditions for the insertion positions of the latch circuits become the following:
(conditions for the insertion position of latch circuit 003)
xe2x80x83Ftpd+D012+Lset less than Tclkxe2x80x83xe2x80x83(5)
Ftpd+D012xe2x89xa71/2xc2x7Tclkxe2x80x83xe2x80x83(6)
(conditions for the insertion position of latch circuit 004)
Ftpd+D012+Ldel+D013+Lsetxe2x89xa63/2xc2x7Tclkxe2x80x83xe2x80x83(7)
Ftpd+D012+Ldel+D013xe2x89xa7Tclkxe2x80x83xe2x80x83(8)
Equations 5 and 6 are the conditions for the insertion position of latch circuit 003, and Equations 7 and 8 are the conditions for the insertion position of latch circuit 004. Therefore, the latch circuit packages A to C in FIG. 8 represent the packaging at the limits satisfying these conditions, the insertion positions of the latch circuits have a permitted width, and the conditions are not as severe as the case of using flip flop circuits. To the extent that these conditions in Equations 5 to 8 are satisfied, the maximum delay of the logic gates can be maintained at the value in Equation 4.
However, in the design of latch circuits, depending on the insertion positions of the latch circuits, the circuits may not be able to tolerate any displacement of the clock edge, and thus if the clock edge is only slightly displaced, an operational error can occur. The displacement of the clock edge occurs due to skew caused by variations in performance of the transistors during the LSI production process and jitter during LSI operations, for example. In addition, the percentage of skew and jitter with respect to the clock cycle becomes large as the operating frequency of LSI increases, and thus forming a circuit that can tolerate displacement of the clock edge is indispensable.
An object of the present invention is to provide a multistage pipeline latch circuit and a manufacturing method for the same that tolerates displacement of the clock edge by utilizing the insertion positions for the latch circuits and timing of the clock input into the latch circuits.
The multistage pipeline latch circuit according to a first aspect of the invention for resolving the above-described problems, provides an input flip flop circuit to which an input signal is applied, an output flip flop circuit that supplies an output signal, and a latch circuit provided between the input and output flip flop circuits, wherein this latch circuit, which operates as a two or more stage pipeline, provides a clock signal supply means that supplies a common clock signal to the input and output flip flop circuits and the latch circuits, and a circuit insertion position selection means that determines the insertion position of the input and output flip flop circuits and the latch circuits such that the input of the latch circuit is defined at the center of the through period of the latch circuit.
In an apparatus constructed in this manner, the insertion position of the input and output flip flop circuit and the latch circuit is determined by the circuit insertion position selection means so that the input of the latch circuit is defined at the center of the through period of the latch circuit, and thus the operation of LSI manufacture is stabilized so that the influence received by the multistage pipeline latch circuit from the Skew due to the variation in the transistor performance, the jitter, and duty ratio that occur during operation of the LSI, etc., is minimized.
Preferably, in a second aspect of the invention, the latch circuit has an LL latch circuit and an LH latch circuit, and the circuit insertion position determination means is structured having as a condition for the LL latch that:
Ftpd+D110=3/4xc2x7Tclkxe2x88x921/2xc2x7Lset,
and having as a condition for the LH latch circuit that:
Ftpd+D110+Ldel+D111=5/4xc2x7Tclkxe2x88x921/2xc2x7Lset.
Here, Ftpd denotes the delay time of the input flip flop circuit; D110 denotes the delay time of the logic gates mounted between input flip flop circuit and the LL latch circuit; D111 denotes the delay time of the logic gates mounted between the LL latch circuit and the LH latch circuit; Lset denotes the set-up time of the LL latch circuit and the LH latch circuit; and Tclk denotes the clock cycle.
The multistage pipeline latch circuit according to a third aspect provides an input flip flop circuit to which a signal is applied, an output flip flop circuit that supplies an output signal, and a plurality of latch circuits provided between the input and output flip flop circuits, wherein said latch circuits, which operate as a pipeline of two or more stages, provide a clock signal supply means that supplies a first clock signal to the input and output flip flop circuits, and a latch circuit clock signal supply means that supplies a fixed clock signal to each of the latch circuits such that the input of the latch circuits is defined at the middle of the through period of the latch circuits.
In a device structured in this manner, a fixed clock signal is supplied to each of the latch circuits by the latch circuit clock signal supply means, and thus even if the positions at which the plurality of latch circuits are provided between the input and output flip flop circuits vary, they are adjusted individually by the latch circuit clock signal supply means, and the operation of LSI manufacture is stabilized so that the influence received by the multistage pipeline latch circuit from the Skew due to the variation in the transistor performance, the jitter, and duty ratio that occur during operation of the LSI, etc. is minimized.
Preferably, as in a fourth aspect of the invention, the latch circuit clock signal supply means is structured so that the clock signals that are output from the clock signal supply means are input to the delay elements, and fixed clock signals are supplied to each of the latch circuits, and thus the delay time of the delay elements can be used as a clock input adjustment means.
In addition, in a fifth aspect of the invention, there is a fist LH latch circuit, an LL latch circuit, and a second LH latch circuit, and the latch circuit clock signal supply means is structured having as a condition for the first LH latch circuit that:
D231=Ftpd+D210xe2x88x921/4xc2x7Tclk+1/2xc2x7Lset,
having as a condition for the LL latch circuit that:
D232=Ftpd+D210+Ldel+D211xe2x88x923/4 xc2x7Tclk+1/2xc2x7Lset,
and having as a condition for the second LH latch circuit that:
D233=Ftpd+D210+Ldel+D211+Ldel+D212xe2x88x925/4xc2x7Tclk+1/2Lset.
Here, Ftpd denotes the delay time of the output flip flop circuit; D210 denotes the delay time for the logic gate mounted between the input flip flop circuit and the first LH latch circuit; D211 is the delay time of the logic gate mounted between the first LH latch circuit and the LL latch circuit; D212 is the delay time of the logic gate mounted between the LL latch circuit and the second LH latch circuit; Ldel is the through delay time of the LL latch circuit and the LH latch circuit; Lset denotes the set-up time for the first and second LH latch circuit and the LL latch circuit; and Tclk denotes the clock cycle.
The multistage pipeline latch circuit according to a sixth aspect provides an input flip flop circuit to which an input signal is applied, an output flip flop circuit that supplies an output signal, and a plurality of latch circuits provided between the input and output flip flop circuits, where said latch circuits, operating as a two or more stage pipeline, provide a clock signal supply means that supplies a first clock signal to an input and output flip flop circuit and a local clock signal supply means that supplies a second clock signal to the latch circuit, and the local clock signal supply means selects the second clock signal input such that the input of the latch signal is defined at the center of the through period for a specific latch in this latch circuit.
In a device structured in this manner, the second clock signal input is adjusted focusing on a particular latch circuit, instead of a being structure that supplies the second clock signal to the latch circuit by the local clock signal supply means, and thus, while this is a simple clock input adjustment, the structure is such that adjusting of other latch circuits can always be carried out by adjusting that particular latch circuit, and the operation of LSI manufacture is stabilized so that the influence received by the multistage pipeline latch circuit from the Skew due to the variation in the transistor performance, the jitter, and duty ratio that occur during operation of the LSI, etc. is minimized.
Preferably, in the seventh aspect, the latch circuit has a first LH latch circuit, an LL latch circuit, and a second LH latch circuit, and the local clock signal supply means has as conditions for the first LH latch circuit the following two equations:
xe2x80x83Skewxe2x89xa6(1/4xc2x7Tclkxe2x88x921/2xc2x7Lset)xe2x88x92|1/2xc2x7Tclkxe2x88x92Ldelxe2x88x92D221|
Skewxe2x89xa6(1/4xc2x7Tclkxe2x88x921/2xc2x7Lset)xe2x88x92|Tclkxe2x88x922xc2x7Ldelxe2x88x92D211xe2x88x92D212|,
has as conditions for the LL latch circuit the following two equations:
Skewxe2x89xa6(1/4xc2x7Tclkxe2x88x921/2xc2x7Lset)xe2x88x92|1/2xc2x7Tclkxe2x88x92Ldelxe2x88x92D211|
Skewxe2x89xa6(1/4xc2x7Tclkxe2x88x921/2xc2x7Lset)xe2x88x92|1/2xc2x7Tclkxe2x88x92Ldelxe2x88x92D212|,
and has as conditions for the second LH latch circuit the following two equations:
Skewxe2x89xa6(1/4xc2x7Tclkxe2x88x921/2xc2x7Lset)xe2x88x92|Tclkxe2x88x922xc2x7Ldelxe2x88x92D211xe2x88x92D212|
Skewxe2x89xa6(1/4xc2x7Tclkxe2x88x921/2xc2x7Lset)xe2x88x92|1/2xc2x7Tclkxe2x88x92Ldelxe2x88x92D212|,
and this structure can select the second clock input conforming to the condition in which the Skew is largest among these six conditions.
Here, D211 denotes the delay time of the logic gate mounted between the first LH latch circuit and the LL latch circuit; D212 is the delay time of the logic gate mounted between the LL latch circuit and the second LH latch circuit; Ldel is the through delay time of the LL latch circuit and the LH latch circuit; Lset is the set-up delay of the first and second LH latch circuits and the LL latch circuit; and Tclk denotes the clock period; and Skew denotes the displacement of the clock.
Preferably, as in the eighth aspect, in the case that the delays of the logic gates of the input and output flip flop circuits and the latch circuits are equal, a particular latch circuit may serve as a latch circuit positioned at the center of the pipeline. In the ninth aspect, the local clock signal supply means can be a structure that inputs to the delay elements the clock signal output by the clock signal supply means, supplies the second clock signal to the latch circuit, and then uses the delay time of the delay elements as a means that adjusts the second clock signal input, which contributes to a reduction in the cost.
A tenth aspect of the multistage pipeline latch circuit provides an input flip flop circuit to which an input signal is applied, an output flip flop circuit that supplies an output signal, and latch circuits provided between the input and output flip flop circuits, wherein the latch circuits, operating as a two or more stage pipeline, provide a clock signal supply means that supplies a common clock signal to the input and output flip flop circuits and the latch circuit, and a logic delay adjusting means that adjusts the delay of the logic gates of the input and output flip flop circuits and the latch circuits such that the input of the latch circuits is defined at the center of the through period of the latch circuit.
An eleventh aspect of the multistage latch circuit provides an input flip flop circuit to which an input signal is applied, an output flip flop circuit that supplies an output signal, and a plurality of latch circuits provided between the input and output flip flop circuits, wherein said latch circuits, operating as a two or more stage pipeline, provide a clock signal supply means that supplies a first clock signal to an input and output flip flop circuit, a latch circuit clock signal supply means that supplies a fixed clock signal to each latch circuit, and a clock input adjusting means that adjusts each clock signal input of each latch circuit such that the input of the latch circuit is defined at the center of the through period of each latch circuit.
A twelfth aspect of the multistage latch circuit provides an input flip flop circuit to which an input signal is applied, an output flip flop circuit that supplies an output signal, and a plurality of latch circuits provided between the input and output flip flop circuits, wherein said latch circuits, operating as a two or more stage pipeline, provide a clock signal supply means that supplies a first clock signal to the input and output flip flop circuits, a local clock signal supply means that supplies a second clock signal to the latch circuits, and a clock input adjusting means that adjusts the second clock signal input such that the input of the latch circuit is defined at the center of the through period with respect to a particular latch circuit among the latch circuits.
In a thirteenth aspect of the invention, a fabrication method for the multistage pipeline that provides an input flip flop circuit to which an input signal is applied, an output flip flop circuit that supplies an output signal, and a latch circuit provided between the input and output flip flop circuits, wherein the fabrication method for a latch circuit, which operates as a two or more stage pipeline, provides a step that selects the clock signal supply circuit that supplies a common clock signal to the input and out flip flop circuits and the latch circuit, and a process that determines the insertion position of the input and output flip flop circuits and the latch circuit such that the input of the latch circuit is defined at the center of the through period of the latch circuit.